As is known, an essential part of the design of a memory is the approach adopted as regards internal timing control, e.g., for timing the read operations.
At present, for devices requiring timing, two approaches are adopted: static and dynamic.
In the static approach, each internal control signal is composed of a succession of events which propagate naturally in response to a given external stimulus. Generally speaking, the static approach provides solely for temporal signal propagation, and is not an actual internal timing, thus greatly simplifying the amount of design work involved. On the other hand, the fully static approach invariably presents drawbacks in terms of high consumption and low speed.
In the dynamic approach, which is normally adopted for memories to overcome the above drawbacks, timing consists in generating appropriate timing signals of given duration, for enabling and disabling corresponding operating steps and so reducing consumption and permitting the use of intrinsically faster circuits. The dynamic approach, however, also presents drawbacks substantially in terms of rigidity and the fact that it fails to allow for any deviation in the reaction rate of the memory elements. As such, in the event of one location deviating noticeably with respect to the average performance of the others, it must be replaced by resorting to redundancy. Alternatively, provision may be made at the design stage for a more relaxed timing, to allow for even considerable differences in the reaction times of the memory elements. Neither solution, however, is wholly satisfactory, in that both waste resources which may be otherwise employed, and slow down the memory considerably.